أنشئ حسابًا أو سجّل الدخول للانضمام إلى مجتمعك المهني.
Latch is sensitive to Clock level so it is level sensitive. For example output of a positive level sensitive latch is equal to input until the clock signal is equals 1 and when clock=0 then the output remains on last value.
FF is edge sensitive Latch which is made by two cascaded latches of different sensitivity. For example the output of a positive edge FF changes on positive edge of clock and remains on that value until next positive clock edge.
The latches and Flip Flops have an important role in all digital logic circuits. Flip Flops (FF) and latches are the sequential logic circuits. They depend on the current input and as well as the previous input. They have memory element and store one bit per one element. The FFs are clocked sequential circuits and latches are clockless sequential circuits. This is the main difference between these two.
