What is Verilog Races and specification?

always @(posedge clk)x = 2;

always @(posedge clk)y = x;

YOU CAN HOLD THE COMMAND BY GIVING THE CONDITION AS THE CLOCK VALUE AND POSEDGE OR NEGEDGE

program can implemented in 3 modules

gate level module

data level module

behavioural moudule

A race condition is a flaw in a system or process that is characterized by an output that exhibits an unexpected dependence on the relative timing or ordering of events. The term originates with the idea of two signals racing each other attempting to influence the output first.

If the order in which the assignment statements or  expressions are exceuted cannot be guaranteed then it is called racism in verilog.

● Active Region – Execute in any order – Blocking Assignments – Evaluate RHS of NBAs – Continuous Assignments – $display ● Inactive Region – #0 Blocking Assignments ● Non-Bloacking Assignment Region – Update the LHS of a NBA statement ● Monitor/Postponed Region – Execute $monitor, $strobe and other PLI calls ● $monitor: used to monitor the changes in the signal list and print them in the format we want whenever there is a change in that signal. ● $strobe: used to prints its arguments arguments at the end of the time-slot in which the $strobe call was executed. ● Scope simulation induced race conditions due to the arbitrary execution order in Active Region ● This is the reason to follow some RTL coding guidelines.

In Verilog certain type of assignments or expression are scheduled for execution at the same time and order of their execution is not guaranteed. This means they could be executed in any order and the order could be change from time to time. This non-determinism is called the race condition in Verilog.

For the purpose of refreshing your memory here is the Verilog execution order again, which we had discussed in a prior post.

Figure : Verilog execution order.

If you look at the active event queue, it has multiple types of statements and commands with equal priority, which means they all are scheduled to be executed together in any random order, which leads to many of the races..

Lets look at some of the common race conditions that one may encounter.

1) Read-Write or Write-Read race condition.

Take the following example :

always @(posedge clk)x = 2;

always @(posedge clk)y = x;

Both assignments have same sensitivity ( posedge clk ), which means when clock rises, both will be scheduled to get executed at the same time. Either first ‘x’ could be assigned value ‘2’ and then ‘y’ could be assigned ‘x’, in which case ‘y’ would end up with value ‘2’. Or it could be other way around, ‘y’ could be assigned value of ‘x’ first, which could be something other than ‘2’ and then ‘x’ is assigned value of ‘2’. So depending on the order final value of ‘y’ could be different.

How can you avoid this race ? It depends on what your intention is. If you wanted to have a specific order, put both of the statements in that order within a ‘begin’…’end’ block inside a single ‘always’ block. Let’s say you wanted ‘x’ value to be updated first and then ‘y’ you can do following. Remember blocking assignments within a ‘begin’ .. ‘end’ block are executed in the order they appear.

always @(posedge clk)beginx = 2;y = x;end

2) Write-Write race condition.

always @(posedge clk)x = 2;

always @(posedge clk)x = 9;

Here again both blocking assignments have same sensitivity, which means they both get scheduled to be executed at the same time in ‘active event’ queue, in any order. Depending on the order you could get final value of ‘x’ to be either ‘2’ or ‘9’. If you wanted a specific order, you can follow the example in previous race condition.

3) Race condition arising from a ‘fork’…’join’ block.

always @(posedge clk)forkx = 2;y = x;join

Unlike ‘begin’…’end’ block where expressions are executed in the order they appear, expression within ‘fork’…’join’ block are executed in parallel. This parallelism can be the source of the race condition as shown in above example.

Both blocking assignments are scheduled to execute in parallel and depending upon the order of their execution eventual value of ‘y’ could be either ‘2’ or the previous value of ‘x’, but it can not be determined beforehand.

4) Race condition because of variable initialization.

reg clk = 0

initialclk = 1

In Verilog ‘reg’ type variable can be initialized within the declaration itself. This initialization is executed at time step zero, just like initial block and if you happen to have an initial block that does the assignment to the ‘reg’ variable, you have a race condition.

There are few other situations where race conditions could come up, for example if a function is invoked from more than one active blocks at the same time, the execution order could become non-deterministic.

-SS.

If there is no certainty of a wire getting value 0 or 1 , means if both 0 or 1 value can be possible , that condition is called race . There are 4 types of race. WRITE-WRITE(writing 2 different value to a single wire or reg at a time )READ-READ race(reading value to 2 different register from single wire at a time )READ-WRITE()WRITE-READ()