VHDL offers several advantages to the system level designer.Some of them are
Standard language
Fully expressive language
Hierarchical
Configurable
Tool availability
Consistency and completeness checks automatic
Tight coupling to lower levels of design
Supports hybrid modeling
Portable
Disadvantages
VHDL is verbose, complicated and confusing
Many different ways of saying the same thing
Constructs that have similar purpose have very different syntax (case vs. select)
Constructs that have similar syntax have very different semantics (variables vs signals)
Hardware that is synthesized is not always obvious (when is a signal a flip-flop vs latch vs combinational)
