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Due to the exploding complexity of digital electronic circuits since the 1970s (see Moore's law), circuit designers needed digital logic descriptions to be performed at a high level without being tied to a specific electronic technology, such as CMOSor BJT. HDLs were created to implement register-transfer level abstraction, a model of the data flow and timing of a circuit.[1]
There are two major hardware description languages: VHDL and Verilog. There are different types of description in them "dataflow, behavioral and structural". Example of dataflow of hdl:
library iEEE; use iEEE.STD_LOGIC_1164.ALL; use iEEE.STD_NUMERIC_STD.ALL; entity not1 is port(a:in STD_LOGIC; b:out STD_logic); end not1; architecture behavioral of not1 is begin b <= not a; end behavioral;
Verilog was one of the first modern[clarification needed] hardware description languages to be invented.[citation needed] It was created by Prabhu Goel and Phil Moorby between late 1983 and early 1984. The wording for this process was "Automated Integrated Design Systems" (later renamed to Gateway Design Automation in 1985) as a hardware modeling language. Gateway Design Automation was purchased by Cadence Design Systems in 1990. Cadence now has full proprietary rights to Gateway's Verilog and the Verilog-XL, the HDL-simulator that would become the de facto standard (of Verilog logic simulators) for the next decade. Originally, Verilog was only intended to describe and allow simulation, the automated synthesis of subsets of the language to physically realizable structures (gates etc) was developed after the language had achieved widespread usage.
Verilog is a portmanteau of the words "verification" and "logic".
A simple example of two flip-flops follows:
module toplevel(clock,reset); input clock; input reset; reg flop1; reg flop2; always @ (posedge reset or posedge clock) if (reset) begin flop1 <= 0; flop2 <= 1; end else begin flop1 <= flop2; flop2 <= flop1; end endmodule
