What is NMOS and PMOS logic?

Logic families discussed so far are the ones that are commonly used for implementing discrete logic functions such as logic gates, flip flops, counters, multiplexers, demultiplexers etc., in relatively less complex digital ICs belonging to the small-scale integration (SSI) and medium-scale integration (MSI) level of inner circuit complexities. The TTL, the CMOS and the ECL logic families are not suitable for implementing digital ICs that have a large-scale integration (LSI) level of inner circuit complexity and above. The competitors for LSI-class digital ICs are the PMOS, the NMOS and the integrated injection logic (I2L). The first two are briefly discussed in this section.

The PMOS logic family uses P-channel MOSFETS. Figure (a) shows an inverter circuit using PMOS logic. MOSFET Q1 acts as an active load for the MOSFET switch Q2. For the circuit shown, GND and −VDD respectively represent a logic ‘1’ and a logic ‘0’ for a positive logic system. When the input is grounded (i.e. logic ‘1’), Q2 remains in cut-off and −VDD appears at the output throughthe conducting Q1.When the input is at −VDD or near −VDD, Q2 conducts and the output goes to near-zero potential (i.e. logic ‘1’).Figure (b) shows a PMOS logic based two-input NOR gate. In the logic arrangement of Fig. (b), the output goes to logic ‘1’ state (i.e. ground potential) only when both Q1 and Q2 are conducting. This is possible only when both the inputs are in logic ‘0’ state. For all other possible input combinations, the output is in logic ‘0’ state, because, with either Q1 or Q2 nonconducting, the output is nearly −VDD through the conducting Q3.

The circuit of Fig.(b) thus behaves like a two-input NOR gate in positive logic. It may be mentioned here that the MOSFET being used as load [Q1 in Fig. (a) and Q3 in Fig. (b)] is designed so as to have an ON-resistance that is much greater than the total ON-resistance of the MOSFETs being used as switches [Q2 in Fig. (a) And Q1 and Q2 in Fig.(b)].

The NMOS logic family uses N-channel MOSFETS. N-channel MOS devices require a smaller chip area per transistor compared with P-channel devices, with the result that NMOS logic offers a higher density. Also, owing to the greater mobility of the charge carriers in N-channel devices, the NMOS logic family offers higher speed too. It is for this reason that most of the MOS memory devices and microprocessors employ NMOS logic or some variation of it such as VMOS, DMOS and HMOS. VMOS, DMOS and HMOS are only structural variations of NMOS, aimed at further reducing the propagation delay. Figures (a), (b) and (c) respectively show an inverter, a two-input NOR and a two-input NAND using NMOS logic. The logic circuits are self-explanatory.

CMOS is the short form for the Complementary Metal Oxide Semiconductor. Complementary stands for the fact that in CMOS technology based logic, we use both p-type devices and n-type devices.

Logic circuits that use only p-type devices is referred to as PMOS logic and similarly circuits only using n-type devices are called NMOS logic. Before CMOS technology became prevalent, NMOS logic was widely used. PMOS logic had also found its use in specific applications.

Lets understand more how NMOS logic works. As per the definition, we are only allowed to use the n – type device as building blocks. No p-type devices are allowed. Lets take an example to clarify this. Following is the truth table for a NOR gate.

Figure : NOR truth table.

We need to come up the a circuit for this NOR gate, using n-mos only transistors. From our understanding  of CMOS logic, we can think about the pull down tree, which is made up of only n-mos gates.

Figure : NOR pulldown logic.

Here we can see that when either of the inputs ‘A’ or ‘B’ is high, the output is pulled down to the ground. But this circuit only reflects the negative logic, or the partial functionality of NOR gate when at least one of the inputs is high. This doesn’t represent the case where both input area low, the first row of the truth table. For an equivalent CMOS NOR gate, there would be pull up tree made up of p-mos devices.

But here we are referring to NMOS logic and we are not allowed to have p-mos devices. How could we come up with the pull up logic for our NOR gate ? The answer is a resistor. Essentially when both n-mos transistor are turned off, we want ‘out’ node to be pulled up and held at VDD. A resistor tied between VDD and ‘out’ node would achieve this. There could be other possible elaborate schemes to achieve the same using n-mos transistors for pulling up purpose, but an n-mos as a resistor is used to pull up the output node.

Of course you see some immediate drawbacks. You can see that when at least one of the pull down n-mos is on, there is a static bias current flowing from VDD to the ground even in the steady state. Which is why such circuits dissipate almost an order of magnitude more power compared to CMOS equivalent. Not only that, this type of circuit is very susceptible to the input noise glitches.

Any n-mos device can be made into a resistor by making it permanently on. N-mos device has inherent resistance and we can achieve the desired resistance by modulating the width of n-mos transistor.

Figure : NMOS logic NOR gate.

The above figure shows the NOR gate made using NMOS logic. Similarly any gate can also be made using PMOS logic.